Furthermore, it uses the serial clock recovery technique to recover the receive clock from the data.
The SIPO block ordinarily has output data latches, a set of data output lines, and a receive clock output. Furthermore, some implementations avoid metastability by making use of a double-buffered register during transfers of data between clock domains. In its simplest form, a PISO has a single shift register that receives the parallel data once per parallel clock and shifts it out at the higher serial clock rate. Also, it uses an external or internal PLL (phase-locked loop) to multiply the incoming parallel clock up to the serial frequency. The PISO block generally has a set of data input lines, input data latches, and a parallel clock input. Furthermore, a SerDes has four distinct architectures: Embedded clock, Parallel clock, Bit interleaved, and 8b/10b. The two functional blocks that comprise a SerDes are the Parallel In Serial Out (PISO) block (Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (Serial-to-Parallel converter). In terms of the build and functionality of a SerDes, it consists of two functional blocks. In summary, a SerDes is a high-speed transmission system that sends signals from the transceiver on one chip to a receiver on another and in the process, converts parallel to serial and back to parallel.
Regarding implementation, SerDes is primarily in use to provide data transmission over a single line or a differential pair, which in turn, minimizes the number of interconnects and input/output pins. Hence the term Serializer/Deserializer, more or less, is a reference to the interfaces in use in the various applications and technologies. Furthermore, these blocks convert data between serial data and parallel interfaces in either direction. In terms of description, a Serializer/Deserializer is a pair of functional blocks commonly in use in high-speed communications to counteract for the limits in the number of inputs and outputs. The transceiver converts parallel data into a serial stream of data that is re-translated into parallel on the receiving end. Serializer/Deserializer is a transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. It may not be exact, but this indeed resembles the functionality of a Serializer/Deserializer (SerDes). Now that serial stream of data is converted back to parallel as it is transmitted. So, let’s see, we have a high-speed transmission of parallel data that is sent to one location and converted into a serial data stream. This process will continue as the second group of ten also has information to route. Moreover, the second set of parallel people will receive all of the serial information collected by my sibling from the original ten people. However, this information path does not end there, because, over the next 30 minutes, this same sibling will have conversed with ten more people. Now, I am not judging here, but I do find this a bit excessive. I know it may not immediately register at first, and that is most likely due to you not looking for the correlation.įor example, I have a high-speed sibling that can easily talk to 10 different people in a phone conversation in a span of 30 minutes. I am sure that I am not the only one that has a relative or two that more or less functions like an electronic device or component that we see in the field of engineering and electronics.